//伪随机数生成器
//四位寄存器Q3——Q0
//右移
//模2加Q3
module random (
    res,
    clk,
    y
);
input clk;
input res;
output y;

reg [3:0] d;//四位寄存器Q3——Q0
assign y=d[0];

always @(posedge clk or negedge res) 
begin
    if (res==0) begin
        d<=4'b1111;
    end else begin
        d[2:0]<=d[3:1];
        d[3]<=d[3]+d[0];            
    end
end
endmodule

//tb
`timescale 1ns/1ps
module random_tb ();
reg clk,res;
wire y;
random random (
    .res(res),
    .clk(clk),
    .y(y)
);
initial begin
    res<=0;
    clk<=0;
    #10 res<=1;
    #5000 $stop;
end
always #1 clk=~clk;
endmodule
